/*
 *  Copyright (C) 2020, Loongson Technology Corporation Limited, Inc.
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
*/

#ifdef CONFIG_LOONGSON_2K300

#ifndef __ASM_MACH_LOONGSON_2K300_H_
#define __ASM_MACH_LOONGSON_2K300_H_

#define PLL_NODE_0_OFFSET 0x0
#define PLL_NODE_1_OFFSET 0x4
#define PLL_DDR_0_OFFSET 0x8
#define PLL_DDR_1_OFFSET 0xc
#define PLL_PIX_0_OFFSET 0x18
#define PLL_PIX_1_OFFSET 0x1c
#define PLL_FREQ_SC 0x20

//6 bit [30:24] odiv 7bit 0x111 1111
#define PLL_GENERIC_0_ODIV_SHIFT 24
#define PLL_GENERIC_0_ODIV_MASK 0x7f

//8 bit [23:15] loopc 9bit 0x1 1111 1111
#define PLL_GENERIC_0_LOOPC_SHIFT 15
#define PLL_GENERIC_0_LOOPC_MASK 0x1ff

//6 bit [14:8] refc 7bit 0x111 1111
#define PLL_GENERIC_0_REFC_SHIFT 8
#define PLL_GENERIC_0_REFC_MASK 0x3f

//6 bit [14:8] 7bit 0x111 1111
#define PLL_GENERIC_1_ODIV_1_SHIFT 8
#define PLL_GENERIC_1_ODIV_1_MASK 0x7f

//6 bit [6:0] 7bit 0x111 1111
#define PLL_GENERIC_1_ODIV_0_SHIFT 0
#define PLL_GENERIC_1_ODIV_0_MASK 0x7f

////////////////////////////////////////

// node and cpu
#define PLL_NODE_0_REFC_SHIFT PLL_GENERIC_0_REFC_SHIFT
#define PLL_NODE_0_REFC_MASK PLL_GENERIC_0_REFC_MASK

#define PLL_NODE_0_LOOPC_SHIFT PLL_GENERIC_0_LOOPC_SHIFT
#define PLL_NODE_0_LOOPC_MASK PLL_GENERIC_0_LOOPC_MASK

#define PLL_NODE_0_ODIV_SHIFT PLL_GENERIC_0_ODIV_SHIFT
#define PLL_NODE_0_ODIV_MASK PLL_GENERIC_0_ODIV_MASK

// i2s and gmac
#define PLL_NODE_1_ODIV_I2S_SHIFT PLL_GENERIC_1_ODIV_1_SHIFT
#define PLL_NODE_1_ODIV_I2S_MASK PLL_GENERIC_1_ODIV_1_MASK

#define PLL_NODE_1_ODIV_GMAC_SHIFT PLL_GENERIC_1_ODIV_0_SHIFT
#define PLL_NODE_1_ODIV_GMAC_MASK PLL_GENERIC_1_ODIV_0_MASK

// ddr pll and ddr
#define PLL_DDR_0_REFC_SHIFT PLL_GENERIC_0_REFC_SHIFT
#define PLL_DDR_0_REFC_MASK PLL_GENERIC_0_REFC_MASK

#define PLL_DDR_0_LOOPC_SHIFT PLL_GENERIC_0_LOOPC_SHIFT
#define PLL_DDR_0_LOOPC_MASK PLL_GENERIC_0_LOOPC_MASK

#define PLL_DDR_0_ODIV_SHIFT PLL_GENERIC_0_ODIV_SHIFT
#define PLL_DDR_0_ODIV_MASK PLL_GENERIC_0_ODIV_MASK

// devs and network
#define PLL_DDR_1_ODIV_DEVS_SHIFT PLL_GENERIC_1_ODIV_1_SHIFT
#define PLL_DDR_1_ODIV_DEVS_MASK PLL_GENERIC_1_ODIV_1_MASK

#define PLL_DDR_1_ODIV_NET_SHIFT PLL_GENERIC_1_ODIV_0_SHIFT
#define PLL_DDR_1_ODIV_NET_MASK PLL_GENERIC_1_ODIV_0_MASK

// pix pll and pix
#define PLL_PIX0_0_REFC_SHIFT PLL_GENERIC_0_REFC_SHIFT
#define PLL_PIX0_0_REFC_MASK PLL_GENERIC_0_REFC_MASK

#define PLL_PIX0_0_LOOPC_SHIFT PLL_GENERIC_0_LOOPC_SHIFT
#define PLL_PIX0_0_LOOPC_MASK PLL_GENERIC_0_LOOPC_MASK

#define PLL_PIX0_0_ODIV_SHIFT PLL_GENERIC_0_ODIV_SHIFT
#define PLL_PIX0_0_ODIV_MASK PLL_GENERIC_0_ODIV_MASK

// gmac bp
#define PLL_PIX0_1_ODIV_GMACBP_SHIFT PLL_GENERIC_1_ODIV_0_SHIFT
#define PLL_PIX0_1_ODIV_GMACBP_MASK PLL_GENERIC_1_ODIV_0_MASK

#define PLL_FREQSCALE_SDIO_SHIFT 24
#define PLL_FREQSCALE_SDIO_MASK 0xf

#define PLL_FREQSCALE_I2S_SHIFT 20
#define PLL_FREQSCALE_I2S_MASK 0xf

#define PLL_FREQSCALE_APB_SHIFT 16
#define PLL_FREQSCALE_APB_MASK 0xf

#define PLL_FREQSCALE_USB_SHIFT 12
#define PLL_FREQSCALE_USB_MASK 0xf

#define PLL_FREQSCALE_BOOT_SHIFT 8
#define PLL_FREQSCALE_BOOT_MASK 0xf

#define PLL_FREQSCALE_PIX_SHIFT 4
#define PLL_FREQSCALE_PIX_MASK 0xf

#define PLL_FREQSCALE_NODE_SHIFT 0
#define PLL_FREQSCALE_NODE_MASK 0xf
/*
 * about clk manager (PLL)
 */

#endif /* __ASM_MACH_LOONGSON_2K300_H_ */
#endif /* CONFIG_LOONGSON_2K300 */
